1. Field of the Invention
This invention relates generally to electromigration test structures and more particularly, it relates to an improved interconnection test structure for evaluating electromigration characteristics in a more accurate and reliable manner.
2. Description of the Prior Art
As semiconductor integrated circuit devices are continuing to be designed with smaller and smaller dimensions so as to accommodate higher integration density such as for VLSI, the metal interconnection lines or wiring are made thinner and longer and the number of such metal interconnection lines is further increasing. Furthermore, in view of the progressive miniaturization of the VLSI semiconductor circuit components and in order to supply electrical current to the high density packed, active regions thereof, two or more metal interconnection levels are required. In addition, the electrical contact between the various metal interconnection levels must be provided through the use of very small holes referred to as "vias," which are typically filled by a metal plug such as tungsten.
As a consequence, the density of the electric current flowing through the vias increases as the integration density increases. This high electric current will cause a diffusion phenomenon to occur referred to as "electromigration" where the metal atoms in the interconnection (metal line) migrate in the same direction as that of the electron movement. When this happens, the resultant metal atom migration will cause an atomic vacancy or void to be formed at the location from which the metal atoms have moved or will cause a hillock to be built up at the location where the metal atoms accumulate. When such voids are formed, the local cross-sectional area of the metal line will be decreased and the local current density in the metal line will be increased, thereby likely to cause a discontinuity or failure of the interconnection. On the other hand, when such hillocks are formed, this may also cause a failure due to a short circuit.
Thus, the electromigration characteristics of the metal conductors (e.g., aluminum, aluminum-alloys, and/or refractory metal) in the semiconductor integrated circuit devices are of a major concern. Accordingly, test methods for evaluating the electromigration resistance of conductors have been developed heretofore. One such traditional test structure 100 that has been adopted by the National Bureau of Standards for determining the electromigration characteristics and thus reliability is illustrated in FIG. 1. Since the entire test structure 100 is located in a single planar surface, this is referred to as a "infinite source" structure.
The electromigration circuit element is comprised of a long, thin metal test conductor or line 102 having larger extension metal conductors 104, 106 joined at each end of the test conductor 102. The larger extension metal conductors 104 and 106 are coupled to an external current source 108 via test or bond pads 110, 112 for applying electrical stressing current to the test conductor 102. The length L of the test conductor 102 is about 800 .mu.m, and the width W thereof is approximately 0.5 .mu.m. The thickness of the test conductor is similar to the CMOS process technology used, such as 1 .mu.m for a 1 micron technology. A pair of narrow transverse conductors 114, 116 are joined adjacent the ends of the test conductor 102. The narrow conductors 114 and 116 are coupled to a grounded voltmeter 118 via test or bond pads 120, 122 for voltage measurements.
Initially, prior to performing the electromigration test the voltmeter 118 is used to measure the resistance of the unstressed test conductor 102 so as to define an "initial" resistance. For the electromigration evaluating test, an electrical stressing current having a specified current density such as about 1.times.10.sup.6 amp/cm.sup.2 is applied for a preselected amount of time to the test conductor 102 via the test pads 110 and 112 by the current source 108 so as to accelerate electromigration. Then, the stressing current is disconnected and the voltage across the test conductor 102 is measured again by the voltmeter via the test pads 120, 122 to determine its resistance.
This process is repeated over and over until there is a "failure" in the test conductor 102. As used herein, the term "failure" can be defined to be an increased resistance of 20 percent from the original unstressed resistance value. Therefore, the life of the interconnection can be estimated from elapsed time that it takes to cause the failure. Further, the test may be performed on the test conductor 102 which is heated to approximately 200.degree. C. to 300.degree. C. in order to accelerate the deterioration of the interconnection. Nevertheless, even under such conditions the typical test may require many weeks or a month before a failure occurs. As a result, this traditional method is not a practical testing method that can be employed.
In order to greatly shorten the testing period, there have been developed more recently several wafer-level electromigration test methods which utilize considerably higher current density and higher temperatures so as to accelerate the electromigration phenomenon in the interconnections. Such electromigration test techniques include those known as TRACE, SWEAT, Isothermal, and BEM. For example, the term "SWEAT" is an acronym for Standard Wafer Level Electromigration Acceleration Test which provides for a much larger current through the test conductor than the conventional "long-term" test. The SWEAT technique requires a typical time of only about 30 seconds at a current density of 1 to 2.times.10.sup.7 amps/cm.sup.2 for an aluminum interconnection. However, the SWEAT test has not been widely accepted in the semiconductor industry due to the lack of correlation between the results produced thereby and the results obtained from the more traditional "long-term" test.
Further, the SWEAT or Isothermal test cannot accurately predict the electromigration characteristics on metal interconnections with a single via, as shown in FIG. 2. It will be noted that the test structure 200 of FIG. 2 is identical to the test structure 100 of FIG. 1, except that it contains a single via 224 disposed adjacent each end of the test conductor 202. Further, the test conductor 202 is formed on a different level than the extension conductors 204, 206; the narrow transverse conductors 214, 216; and test pads 210, 212, 220, 222. Accordingly, the test structure 200 of FIG. 2 is used to simulate a high-density semiconductor integrated circuit fabricated with multiple levels of metal interconnections in which metal-filled vias are electrically coupling the various metal interconnection layers. Since the test structure 200 is not contained in a single planar surface, it is referred to as a "finite source" structure.
As previously pointed out, the vias 224 are typically filled with a metal plug which is a refractory material such as tungsten. However, the physical properties of tungsten are substantially different from the physical properties of aluminum or aluminum-alloys forming the metal interconnection line 202. Further, the dimensions of the vias 224 are extremely small and deep and are generally smaller than the metal interconnection line 202. Thus, the test structure 200 of FIG. 2 with a single via 224 located adjacent each end of the test conductor 202 will create a current crowding effect on the via region of the test conductor which leads to electromigration enhancement of the metal near the via. Also, when high current stressing is employed, the via region will experience electromigration failure before the electromigration failure of the metal interconnection line. Further, the area underneath the via may also fail initially before the electromigration failure of the metal interconnection line due to the intersection of grain boundaries (triple point).
Therefore, there is still a need for an interconnection test structure for evaluating accurately and reliably electromigration characteristics. Further, it will be expedient that the high current stressing performed on the wafer-level be capable of being correlated so as to predict electromigration characteristics in low current stressing performed on a fully assembled package chip.